basic principle of pass transistor circuits

3.1 INTRODUCTION

Dynamic logic circuits offer several advantages in realizing high-density, high performancedigital system where reduction of circuit delay and silicon area is important. Operation of alldynamic logic gates depend on temporary storage of charge in parasitic node capacitances,instead of relying on steady-state circuit behavior. Dynamic logic circuits require periodicclock signals in order to control charge refreshing.Dynamic logic techniques save area by reducing the number of transistors per gate,and save power by reducing the number of gates and the static current in structures such asflip-flops & shift registers. Dynamic CMOS circuits save chip area while enhancing speedover conventional CMOS circuits, but precautions must be taken to ensure proper operation.Use of common clock signals the system enables synchronize the operation of various circuitblocks. Capability of temporarily storing a state at a capacitive node allows implementingsimple sequential circuits with memory functions.Disadvantage of dynamic storage is the use of small-sized, leaky capacitors forstoring logic values. They must be clocked at a minimum operating frequency in order tomaintain their charge.

3.1.1 Dynamic D-Latch

The Dynamic D-latch circuit is shown in figure 3.1. Parasitic input capacitance Cx plays animportant role in dynamic operation of circuit. Input pass transistor is driven by externalclock signal. When CK = 1, MP turns on, Cx charged or discharged through MP, dependingon D voltage level, Q assumes same logic level as input. When CK = 0, MP turns off, Cx isisolated from D, amount charge stored in Cx during last cycle determines output voltagelevel Q.

Figure 3.1:

Dynamic D-latch

3.2 PRINCIPLES OF PASS TRANSISTOR CIRCUITS

3.2.1 Basic Principles of Pass Transistor Circuits

The fundamental building block of dynamic logic circuits, consisting of an nMOS passtransistor, MP driving the gate of another nMOS transistor is shown in figure 3.2. The passtransistor, MP is driven by periodic clock signal and acts as access switch to either to chargeup or down the parasitic capacitance Cx, depending on Vin.

 Figure 3.2:

nMOS Dynamic D-latchTwo operations are possible when CK = 1. Logic ‘1’ transfer and logic ‘0’ transfer.The output of depletion-load nMOS inverter depends on voltage Vx. MP provides onlycurrent path to the intermediate capacitive node (soft node) X. When CK = 0, the MP ceasesto conduct and charge stored in the parasitic capacitor Cx continues to determine output levelof the inverter.

3.2.2 Logic ‘1’ Transfer

If the soft node voltage is equal to 0 initially, i.e., Vx(t = 0) = 0 V. Logic ‘1’ level is appliedto the input terminal, which corresponds to Vin = VDD. When CK changes from 0 to 1, MPwill be in saturation. The equivalent circuit for logic ‘1’ transfer is shown in figure 3.3.

Figure 3.3:

Equivalent circuit for logic ‘1’ transferThe pass transistor MP operating in the saturation region starts to charge up thecapacitor Cx, since, I = C dV/dt. Thus,Above equation can be solved for Vx(t), as follows

Variation of node voltage Vx w.r.t. last equation is plotted as a function of time isshown in figure 3.4.

Figure 3.4:

Variation of node voltage as a function of time during logic ‘1’ transfer.The fact that the node voltage Vx has an upper limit of Vmax = (VDD – VT,n) hassignificant implication for circuit design.

Pass transistors in series:

The node voltages in the pass transistor chain during logic ‘1’ transfer are as shown in thefigure 3.5.

Figure 3.5:

Node voltages in a pass transistors chain during logic ‘1’ transfer.With threshold voltage of all transistors are same, the node voltage at the end of thepass transistor chain will become one threshold voltage lower than VDD, regardless of number of pass transistors in chain.

Pass transistors driving gate of another Pass transistors:

Node voltages during the logic ‘1’ transfer, when each pass transistor is driving another passtransistor are as shown in figure 3.6. In designing nMOS pass transistors logic, one mustnever drive a pass transistor with the output of another pass transistor.

Figure 3.6:

Node voltages during logic ‘1’ transfer, when each pass transistors is drivinganother pass transistor.